Communication flows in power-efficient Networks-on-Chips

Networks-on-Chips (NoCs) represent a scalable wiring solution for future chips, with dynamic allocation-based networks able to provide good utilisation of the scarce available resources. This thesis develops power-efficient, dynamic, packet-switched NoCs which can support onchip communication flows. Given the severe power constraint already present in VLSI, a power efficient NoC design direction is first developed. To accurately explore the impact of various design parameters on NoC power dissipation, 4 different router designs are synthesised, placed and routed in a 90nm process. This demonstrates that the power demands are dominated by the data-path and not the control-path, leading to the key finding that, from the energy perspective, it is justifiable to use more computation to optimise communication. A review of existing research shows the near-ubiquitous nature of stream-like communication flows in future computing systems – making support for flows within NoCs critically important. It is shown that in several situations, current NoCs make highly inefficient use of network resources in the presence of communication flows. To resolve this problem, a scalable mechanism is developed to enable the identification of flows – with a flow defined as all packets going to the same destination. The number of virtual-channels that can be used by a single flow is then limited to the minimum required, ensuring efficient resource utilisation. The issue of fair resource allocation between flows is next investigated. The locally fair, packet-based allocation strategies of current NoCs are shown not to provide fairness between flows. The mechanism already developed to identify flows by their destination nodes is extended to enable flows to be identified by source-destination address pairs. Finally, a modification to the link scheduling mechanism is proposed to achieve max-min fairness between flows.